Publications

Journals:

  1. Jaberipur, G., “A Generic Modulo  Adder Based on Stored Negabit Representation of Residues,” Journal of Computer Science and Engineering, to appear.

  2. Gorgin, S., and G. Jaberipur, “Design and Synthesis of High Speed Low Power Signed Digit Adders,” Journal of Iranian Association of Electrical and Electronics Engineering, Vol. 7, No. 2, pp 7-14, Fall & Winter 2010.

  3. A. Kaivani and G. Jaberipur, “Decimal CORDIC Rotation based on Selection by Rounding,” The Computer Journal, Oxford Journal, Vol. 54, No. 11, pp. 1798-1809 2011 [pdf].

  4. A. Kaivani, A. Hosseiny, G. Jaberipur, “Improving the Speed of Decimal Division,” IET Computer & Digital Techniques, Vol. 5, lss. 5, pp. 393-404 [pdf].

  5. Jaberipur, G. and S. Gorgin, “An improved maximally redundant signed digit adder,”  Computers & Electrical Engineering, Vol. 36, No. 3, pp 491-502, May 2010. [pdf]

  6. Jaberipur, G., B. Parhami and S. Gorgin, "Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value," IEEE Trans. on Computers, Vol. 59,  No. 5, pp 694-706, May 2010 [pdf].

  7. Gorgin, S. and G. Jaberipur, “A Fully Redundant Decimal Adder and its Application in Parallel Decimal Multipliers,” The Micro Electronics Journal, Vol. 40, No. 10, pp. 1471-1481, October, 2009. [pdf]

  8. Kaivani, A., G. Jaberipur, “Fully Redundant Decimal Addition and Subtraction Using Stored Unibit Encoding,” Integration, the VLSI Journal, Vol. 43, No. 1, January 2010, pp 34-41 [pdf].

  9. Jaberipur G., Amir Kaivani, “Improving the Speed of Parallel Decimal Multiplication,” IEEE Trans. on Computers, Vol. 58, No. 11, pp. 1539-1552, November 2009. [pdf]

  10. Jaberipur, G "A One-step modulo 2n+1 Adder Based on Double-lsb Representation of Residues,” The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2&4, 2006. Pp 10-16 (published in Fall 2008). [pdf]

  11. Jaberipur, G. and B. Parhami, "Constant-Time Addition with Hybrid-Redundant Numbers: Theory and Implementations," Integration, the VLSI Journal, Vol. 41 No. 1, January 2008, PP. 49–64. [pdf]

  12. Jaberipur, G. and A. Kaivani, "Binary-Coded Decimal (BCD) Digit-Multipliers," IET Computers, and Digital Techniques, Vol.1, No. 4, pp. 377-381, July 2007. [pdf]

  13. Jaberipur, G. and B. Parhami, "Stored-Transfer Representations with Weighted Digit-Set Encodings for Ultrahigh-Speed Arithmetic," IET Circuits, Devices, and Systems, Vol. 1, No. 1, pp. 102-110, February 2007. [pdf]

  14. Jaberipur, G., B. Parhami, and M. Ghodsi, “An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding,” Journal of VLSI Signal Processing, Vol. 42, No. 2, pp. 149-158, February 2006. (Reprints available on request from the first author). [pdf]

  15. Jaberipur, G., B. Parhami, and M. Ghodsi, “Weighted Two-Valued Digit-Set Encodings: Unifying Efficient Hardware Representation Schemes for Redundant Number Systems,” IEEE Transaction on Circuits and Systems I, Vol. 52, No. 7, pp. 1348-1357, July 2005.
    [pdf]

  16. Jaberipur, G. and M. Ghodsi, “High Radix Signed Digit Number Systems: Implementation Paradigms,” Scientia Iranica, Volume 10, Number 4, pp. 383-391, October 2003.
    [pdf]

  17. Jaberipur, G. “پردازش کارآ: نیاز اساسی استاندارد کردن رمز تبادل اطلاعات فارسی,”, Gosaresh-Computer, No. 76, page 19, 1986 (English translation of the title: Efficient Processing: A Central Goal in Standardizing the Persian Information Exchange Code)

  18. Jaberipur, G. “یک راه حل ساده برای مرتب کردن اطلاعات فارسی,” Gosaresh-Computer, No. 74, page 3, 1985 (English translation of the title: A Simple Solution for Sorting Persian Data)

  19. Jaberipur, G., “فارسی­سازی زبان­های برنامه­سازی,” Gosaresh-Computer, No. 68, page 5, 1985 (English translation of the title: Realizing the Persian Version of Programming Languages)

      Conferences:

  1. Gorgin S. and G. Jaberipur, “A Family of Signed Digit Adders,” in Proc. of the 20th IEEE Symposium on Computer Arithmetic, pp. 112-120, July, 25-27, 2011, Tubingen, Germany.

  2. Jaberipur, G. and S. Nejati, “Balanced Minimal Latency RNS Addition for Moduli Set {2n − 1, 2n, 2n + 1},” in Proc. of the 18th International Conference on Systems, Signals, and Image Processing, PP. 159-165, 16-18, June 2011, Sarajevo, Bosnia and Herzegovina.

  3. Jaberipur, G. and B. Parhami, “Posibits, Negabits, and Their Mixed Use in Efficient Realization of Arithmetic Algorithms”, in Proc. of the 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), pp. 3-9, Sep. 2010.

  4. Jaberipur, G. and H. Alavi, “A Modulo 2n+1 Multiplier with Double-LSB Encoding of residues”, in Proc. of the 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS), pp. 147-150, Sep. 2010.

  5. Gorgin S., G. Jaberipur, and B. Parhami, “Design and Evaluation of Decimal Array Multipliers," in Proc. of the  ASILOMAR 2009, pp. 1782-1786, USA. [pdf]

  6. Jaberipur G. B. Parhami, “Unified Approach to the Design of Modulo-(2n ± 1) Adders Based on Signed-LSB Representation of Residues,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 57-64, Jun. 8-10, 2009, Portland, USA. [pdf]

  7. Gorgin S., G. Jaberipur, “Fully Redundant Decimal Arithmetic,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 145-152, Jun. 8-10, 2009, Portland, USA. [pdf]

  8. Jaberipur, G and S. Gorgin, “A High Speed Low Power Signed Digit Adder,” in Proc. of the 16th Iranian Conference on Electrical Engineering, Tarbiat Modares University, Tehran, Iran, May 13-15, 2008. [pdf] 

  9. Jaberipur, G., S. Gorgin, “A Nonspeculative One-Step Maximally Redundant Signed Digit Adder,” in Proc. of the 13th int,l CSI Computer Conference, Kish island, Persian Gulf, Iran, March, 9-11, 2008.Also printed in Lecture Notes on Computer Science, CSICC 2008, CCIS 6, pp. 235–242, 2008. [pdf]

  10. Sheikhattar, H., V. Rahiman, G. Jaberipur and N. Noroozi, “Design and Implementation issues for the MobFish,” in Proc. of the Twelfth International Conference on Distributed Multimedia Systems, Grand Canyon, USA, Aug. 30, Sep. 1, 2006.

  11. Jaberipur, G., B. Parhami, and M. Ghodsi, “Weighted Bit-Set Encodings for Redundant Digit Sets: Theory and Applications,” in Proc. of the 36th Asilomar Conf. Signals Systems and Computers, pp. 1629-1633, November 2002. [pdf]

  12. Jaberipur, G., B. Parhami, and M. Ghodsi, “A Class of Stored-Transfer Representations for Redundant Number Systems,” in Proc. of the 35th Asilomar Conf. Signals Systems and Computers, Nov. 2001, pp. 1304-1308. [pdf]

  13. Ghodsi, M., G. Jaberipur and R. Khosravi, “SADL: A Systolic Array Description Language,” in Proc. of the 4th CSI Computer Conference (CSICC'98), Sharif University of Technology, Jan. 1999. (in Persian)

        Web Documents:

  • Jaberipur, G., H. Alavi, “Comment on Fast Parallel Prefix Modulo 2n+1 Adder by Costas Efstathiou et al, IEEE Trans. Computers, Vol. 53, No. 9 pp. 1211-1216,” [PDF]

Reviewing services for:

  • IEEE Transactions on Computers

  • IEEE Transactions on Circuits and Systems I

  • IEEE Transactions on VLSI

  • Integration, the VLSI Journal

  • IEEE Signal Processing Letters

  • Micro Electronics Journal

  • The Computer Journal

  • 20th IEEE Symposium on Computer Arithmetic

  • IEEE Journal on Emerging and Selected Topics in Circuits and Systems

  • Computer and Electrical Engineering Journal