Publications

Journals:

  1. Jaberipur, G., B. Parhami and S. Gorgin "Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value," IEEE Trans. on Computers, to appear. [PDF]

  2. Gorgin, S. and G. Jaberipur, “A Fully Redundant Decimal Adder and its Application in Parallel Decimal Multipliers,” The Micro Electronics Journal, Vol. 40, No. 10, pp. 1471-1481, October, 2009.[PDF]

  3. Kaivani, A., G. Jaberipur, “Fully Redundant Decimal Addition and Subtraction Using Stored Unibit Encoding,” Integration, the VLSI Journal, to appear. [PDF]

  4. Jaberipur G., Amir Kaivani, “Improving the Speed of Parallel Decimal Multiplication,” IEEE Trans. on Computers, Vol. 58, No. 11, pp. 1539-1552, November 2009. [PDF]

  5. Jaberipur, G "A One-step modulo 2n+1 Adder Based on Double-lsb Representation of Residues,” The CSI Journal on Computer Science and Engineering, Vol. 4, No. 2&4, 2006. Pp 10-16 (published in Fall 2008). [PDF]

  6. Jaberipur, G. and B. Parhami, "Constant-Time Addition with Hybrid-Redundant Numbers: Theory and Implementations," Integration, the VLSI Journal, Vol. 41 No. 1, January 2008, PP. 49–64. ·[PDF]

  7. Jaberipur, G. and A. Kaivani, "Binary-Coded Decimal (BCD) Digit-Multipliers," IET Computers, and Digital Techniques, Vol.1, No. 4, pp. 377-381, July 2007. [PDF]·

  8. Jaberipur, G. and B. Parhami, "Stored-Transfer Representations with Weighted Digit-Set Encodings for Ultrahigh-Speed Arithmetic," IET Circuits, Devices, and Systems, Vol. 1, No. 1, pp. 102-110, February 2007. [PDF]·

  9. Jaberipur, G., B. Parhami, and M. Ghodsi, “An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding,” Journal of VLSI Signal Processing, Vol. 42, No. 2, pp. 149-158, February 2006. (Reprints available on request from the first author). [PDF]

  10. Jaberipur, G., B. Parhami, and M. Ghodsi, “Weighted Two-Valued Digit-Set Encodings: Unifying Efficient Hardware Representation Schemes for Redundant Number Systems,” IEEE Transaction on Circuits and Systems I, Vol. 52, No. 7, pp. 1348-1357, July 2005. [PDF]

  11. Jaberipur, G. and M. Ghodsi, “High Radix Signed Digit Number Systems: Implementation Paradigms,” Scientia Iranica, Volume 10, Number 4, pp. 383-391, October 2003. [PDF]

  12. Jaberipur, G. “Efficient Processing: A Vital Goal in Standardizing the Persian Information Exchange Code”, Gosaresh-Computer, No. 76, page 19, 1986 (in Persian)

  13. Jaberipur, G. “A Simple Solution for Sorting Persian Data”, Gosaresh-Computer, No. 74, page 3, 1985 (in Persian)

  14. Jaberipur, G., “Realizing the Persian Version of Programming Languages”, Gosaresh-Computer, No. 68, page 5, 1985 (in Persian)

 

Conferences:

  1.  Jaberipur G. B. Parhami, “Unified Approach to the Design of Modulo-(2n ± 1) Adders Based on Signed-LSB Representation of Residues,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 57-64, Jun. 8-10, 2009, Portland, USA. [PDF]


  2.  Gorgin S., G. Jaberipur, “Fully Redundant Decimal Arithmetic,” in Proc. of the 19th IEEE Symposium on Computer Arithmetic, pp. 145-152, Jun. 8-10, 2009, Portland, USA. [PDF]

  3. Jaberipur, G and S. Gorgin, “A High Speed Low Power Signed Digit Adder,”The 16th Iranian Conference on Electrical Engineering, Tarbiat Modares University, Tehran, Iran, May 13-15, 2008. [PDF]

  4. Jaberipur, G., S. Gorgin, “A Nonspeculative One-Step Maximally Redundant Signed Digit Adder,”The 13th int,l CSI Computer Conference, Kish island, Persian Gulf, Iran, March, 9-11, 2008.Also printed in Lecture Notes on Computer Science, CSICC 2008, CCIS 6, pp. 235–242, 2008. [PDF]

  5. Sheikhattar, H., V. Rahiman, G. Jaberipur and N. Noroozi, “Design and Implementation issues for the MobFish,” The Twelfth International Conference on Distributed Multimedia Systems, Grand Canyon, USA, Aug. 30, Sep. 1, 2006.

  6. Jaberipur, G., B. Parhami, and M. Ghodsi, “Weighted Bit-Set Encodings for Redundant Digit Sets: Theory and Applications,” Proc. 36th Asilomar Conf. Signals Systems and Computers, pp. 1629-1633, November 2002. [PDF]

  7. Jaberipur, G., B. Parhami, and M. Ghodsi, “A Class of Stored-Transfer Representations for Redundant Number Systems,” Proc. 35th Asilomar Conf. Signals Systems and Computers, Nov. 2001, pp. 1304-1308. [PDF]

  8. Ghodsi, M., G. Jaberipur and R. Khosravi, “SADL: A Systolic Array Description Language,” Proceedings of 4th CSI Computer Conference (CSICC'98), Sharif University of Technology, Jan. 1999. (in Persian)

Web Documents:

    Jaberipur, G., H. Alavi, “Comment on Fast Parallel Prefix Modulo 2n+1 Adder by Costas Efstathiou et al, IEEE Trans. Computers, Vol. 53, No. 9 pp. 1211-1216,” [PDF]

 

Review services for:

  • IEEE Transactions on Computers

  • IEEE Transactions on Circuits and Systems I

  • IEEE Transactions on VLSI

  • Integration, the VLSI Journal

  • IEEE Signal Processing Letters

  • Micro Electronics Journal